Integrated circuit devices typically include a number of active devices, such as transistors formed in a substrate, such as a silicon (Si) wafer, that are separated from one another by isolation structures. Isolation structures help to ensure that active devices can be individually controlled by preventing current flow between adjacent devices. Without sufficient isolation, leakage paths can occur between active devices, leading to a number of undesirable effects.
One commonly employed structure used to isolate elements in an integrated circuit is a shallow trench isolation (STI) structure. FIG. 1 shows a cross-sectional side view of a STI structure formed according a conventional method. Referring to FIG. 1, a typical STI structure 100 includes relatively deep trenches formed in a semiconductor wafer or substrate 102 filled with a deposited silicon-oxide (SiO2) 104 to isolate adjacent active areas 106a, 106b. STI has gained popularity because it allows for higher device density than LOCOS isolation. Shallow trench isolation, however, is not without its share of problems.
In particular, conventional methods or processes of forming a STI structure 100 involve depositing a pad oxide 108 and LPCVD (low pressure chemical vapor deposition) nitride layer (not shown in FIG. 1). The LPCVD nitride layer is patterned using a resist and conventionally photolithography techniques to form a hardmask or Field Oxide Mask. A Field Oxide Mask etch is used to etch through the nitride layer, the pad oxide 108 and gouge into the substrate 102, and any remaining resist stripped or ashed in an oxygen (O2) strip. The deep STI trenches are then etched into the substrate 102 using the LPCVD nitride layer as a Field Oxide Mask, and the STI trenches filled with the deposited SiO2 104. Typically, as shown in FIG. 1, a liner oxide 110 is grown on exposed surface of the deep STI trenches prior to filling with the deposited SiO2 104. Finally, the LPCVD nitride layer is stripped to yield the intermediate structure shown in FIG. 1 in which active regions 106a and 106b are separated by STI structures 100.
One problem with conventional STI structures 100 and methods for forming the same is variation in pad oxide 108 thicknesses. Pad oxide thickness is especially critical for transistor threshold voltage (Vt) variation since channel and well implants are done through the pad oxide after the LPCVD nitride layer has been stripped. There are a number of causes for the variation in pad oxide 108 thickness, including variation of nitride to oxide selectivity across the bathlife of a phosphoric bath used to strip the LPCVD nitride layer. For example, in some process flows pad oxide thickness can vary from 70 Å to 135 Å depending on the bathlife of the phosphoric bath. By bathlife it is meant the number of substrates or lots or batches of substrates previously processed in the bath.
Another cause of variation in pad oxide 108 thicknesses arises from tendency of existing LPCVD batch processing techniques to deposit an undesired LPCVD nitride layer on a backside of the substrate. This backside LPCVD nitride layer if not removed generates stresses in the substrate due to coefficient of thermal expansion mismatches that can damage if not destroy the substrate. Typically, the backside LPCVD nitride layer is removed in the phosphoric bath at the same time the front side LPCVD nitride layer is stripped. However, this requires an overetch, which, depending on bathlife, further exacerbates loss or variation in pad oxide 108 thickness.
Finally, due to batch processing and long deposition time of LPCVD nitride deposition in a furnace, there is lack of flexibility of controlling different nitride thicknesses for various process applications. It will be appreciated that this variation in nitride thicknesses can lead to variation in pad oxide 108 thicknesses independent of bathlife.
Another problem with conventional methods for forming STI structures 100 is defectivity. In particular, the LPCVD nitride layer, which is used as a hardmask for forming the deep STI trenches, is deposited in a furnace, does not meet particle and defectivity requirements as devices shrink to smaller line widths.
Prior efforts to avoid some of the above problems with LPCVD nitride by using PECVD (plasma enhanced chemical vapor deposition) nitride have not proven successful. In particular, conventional methods for forming STI structures utilize an in-situ O2 strip to strip any remaining resist following nitride mask open etch which can lead to nitride pinch-off in which the oxide underlying the nitride is under, leading in some instances to a loss of the nitride altogether, and significantly damaging the field oxide mask. An example, of nitride pinch-off is illustrated in FIG. 5, where FIG. 5 is a diagram illustrating an electron microscope image of a sectional side view of a portion of a substrate showing an intermediate structure in a conventional STI fabrication process formed with PECVD nitride and exhibiting nitride pinch-off.
Accordingly, there is a need for a STI structure and a method of forming the same, which significantly reduces variations in pad oxide thickness, and defects in the nitride layer, thereby enabling tailoring of the hardmask dimensions as devices are scaled. There is a further need for an STI process that reduces or eliminates nitride formation on the backside of the substrate, which requires a pad oxide damaging overetch, while substantially avoiding potentially field oxide mask damaging nitride pinch-off.
The present invention provides a solution to these and other problems, and offers further advantages over conventional STI structures and methods of forming the same.